AMD Zynq™ UltraScale+™ MPSoC
Bei Promwad sind wir auf die Entwicklung von SoC-basierter Hardware mit unübertroffenen Integrationsmöglichkeiten spezialisiert, um höchste Leistung und Produktivität zu erzielen.
Durch die Partnerschaft mit den führenden Chipdesign-Unternehmen erhalten wir Zugang zu den marktbesten Lösungen des SoC wie Zynq UltraScale+ MPSoC.
Daniil Samoshchenko, Leiter der Abteilung Partnerschaften bei Promwad
Über Zynq UltraScale+
Die AMD Zynq™ UltraScale+™ MPSoC-Familie basiert auf der AMD UltraScale+™ MPSoC-Architektur. Diese Produktfamilie integriert eine funktionsreiche 64-Bit-Quad-Core- oder Dual-Core-Arm CortexTM-A53- und Dual-Core-Arm Cortex-R5-basierte Prozessorsystem- (PS) und Xilinx Programmable Logic (PL) UltraScale-Architektur in einem einzigen Gerät . Ebenfalls enthalten sind On-Chip-Speicher, externe Multiport-Speicherschnittstellen und eine Vielzahl von Schnittstellen für periphere Konnektivität.
Zielmärkte: Überwachung, Computer Vision, drahtlose 5G-Kommunikation, Augmented Reality (AR), fortschrittliche Fahrerassistenzsysteme (ADAS), industrielles IoT, medizinische Bildgebung
Unsere Leistungen
Elektronisches Hardware-Design mit Zynq UltraScale+
Erstellen Sie Hardware mit Zynq UltraScale+ -Modulen
Linux-Treiberentwicklung und Linux-Anpassung
Benutzerdefinierte IP-Core-Entwicklung für Zynq UltraScale +, Hochgeschwindigkeitsschnittstellen
Unsere Projekte
Zynq UltraScale+ 1G Ethernet
Eine Implementierung des UDP-Protokolls mit Hardware-Gigabit-Ethernet-Controller (GEM). Die Daten werden sowohl von PL- als auch von PS-Subsystemen übertragen.
- Hardware-UDP-Offloader
- AXI4-Stream-Datenschnittstellen
- Steuertreiber für RPU
- Paketrouting zwischen PL und PS über den IP-Port
Zynq UltraScale+ 10G Ethernet
Eine Hardware-Implementierung des UDP-Protokolls und des 10G-MAC.
- Hardware 10G UDP-Offloader
- AXI4-Stream-Datenschnittstellen
JESD204b Datenübertragung nach Linux
Ein Design für die Erfassung und das Streaming von Hochgeschwindigkeits-ADC und -DAC vom / zum PS DDR4-Speicher. Das Subsystem wird unter Linux-Anwendungssteuerung ausgeführt.
10G TCP / IP unter Linux
Das Design löst das Problem der zuverlässigen Datenübertragung von PL zum Server. Daten werden direkt von PS DDR4 über das TCP / IP-Protokoll übertragen. Die erreichte Bandbreite beträgt 3,5 GB über eine 10-G-Schnittstelle.
Warum auf Zynq UltraScale+ entwickeln?
Performance
Die Lösung übertrifft die Leistung von Xilinx 700 um das bis zu Fünffache und bietet aufgrund der heterogenen Verteilung der Arbeitslast und der Speicherbandbreite die beste Leistung pro Watt auf dem Markt.
Produktivität
AMD bietet eine vertraute Umgebung für C / C ++ - Entwickler, Betriebssystemunterstützung und schnelle Implementierung durch Referenzdesign, wodurch die Produktivität bei der Software- und Hardwareentwicklung erhöht wird.
Optimierung
AMD Zynq UltrSscale + verfügt über eine innovative ARM + FPGA-Architektur, ein umfangreiches Betriebssystem, Middleware, Stacks, Beschleuniger und ein IP-Ökosystem. Die Lösung bietet mehrere Ebenen der Hardware- und Software-Sicherheit.
Processing System (PS)
Arm Cortex-A53 Based Application Processing Unit (APU)
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Quad-core or dual-core
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CPU frequency: Up to 1.5GHz
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Extendable cache coherency
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Armv8-A Architecture
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64-bit or 32-bit operating modes
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TrustZone security
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A64 instruction set in 64-bit mode, A32/T32 instruction set in 32-bit mode
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- NEON Advanced SIMD media-processing engine
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Single/double precision Floating Point Unit (FPU)
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CoreSightTM and Embedded Trace Macrocell (ETM)
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Accelerator Coherency Port (ACP)
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AXI Coherency Extension (ACE)
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Power island gating for each processor core
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Timer and Interrupts
- Arm Generic timers support
- Two system level triple-timer counters o One watchdog timer
- One global system timer
- Caches
- 32KB Level 1, 2-way set-associative instruction cache with parity (independent for each CPU)
- 32KB Level 1, 4-way set-associative data cache with ECC (independent for each CPU)
- 1MB 16-way set-associative Level 2 cache with ECC (shared between the CPUs)
Dual-core Arm Cortex-R5 Based Real-Time Processing Unit (RPU)
- CPU frequency: Up to 600MHz • Armv7-R Architecture
- A32/T32 instruction set
- Single/double precision Floating Point Unit (FPU)
- CoreSightTM and Embedded Trace Macrocell (ETM)
- Lock-step or independent operation
- Timer and Interrupts:
- One watchdog timer
- Two triple-timer counters
- Caches and Tightly Coupled Memories (TCMs)
- 32KB Level 1, 4-way set-associative instruction and data cache with ECC (independent for each CPU)
- 128KB TCM with ECC (independent for each CPU) that can be combined to become 256KB in lockstep mode
On-Chip Memory
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256KB on-chip RAM (OCM) in PS with ECC
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Up to 36Mb on-chip RAM (UltraRAM) with ECC in PL
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Up to 35Mb on-chip RAM (block RAM) with ECC in PL
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Up to 11Mb on-chip RAM (distributed RAM) in PL
Arm Mali-400 Based GPU
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Supports OpenGL ES 1.1 and 2.0
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Supports OpenVG 1.1
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GPU frequency: Up to 667MHz
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Single Geometry Processor, Two Pixel Processors
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Pixel Fill Rate: 2 Mpixels/sec/MHz
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Triangle Rate: 0.11 Mtriangles/sec/MHz
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64KB L2 Cache
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Power island gating
Platform Management Unit
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Power gates PS peripherals, power islands, and power domains
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Clock gates PS peripheral user firmware option
External Memory Interfaces
- Multi-protocol dynamic memory controller
- 32-bit or 64-bit interfaces to DDR4, DDR3, DDR3L, or LPDDR3 memories, and 32-bit interface to LPDDR4 memory
- ECC support in 64-bit and 32-bit modes
- Up to 32GB of address space using single or dual rank of 8-, 16-, or 32-bit-wide memories
- Static memory interfaces
- eMMC4.51 Managed NAND flash support o ONFI3.1 NAND flash with 24-bit ECC
- 1-bit SPI, 2-bit SPI, 4-bit SPI (Quad-SPI), or two Quad-SPI (8-bit) serial NOR flash
8-Channel DMA Controller
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Two DMA controllers of 8-channels each
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Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and scatter-gather transaction support
Serial Transceivers
- Four dedicated PS-GTR receivers and transmitters supports up to 6.0Gb/s data rates
- Supports SGMII tri-speed Ethernet, PCI Express® Gen2, Serial-ATA (SATA), USB3.0, and DisplayPort
Dedicated I/O Peripherals and Interfaces
- PCI Express — Compliant with PCIe® 2.1 base specification
- Root complex and End Point configurations
- x1, x2, and x4 at Gen1 or Gen2 rates
- SATA Host
- 1.5, 3.0, and 6.0Gb/s data rates as defined by SATA Specification, revision 3.1
- Supports up to two channels
- DisplayPort Controller
- Up to 5.4Gb/s rate
- Up to two TX lanes (no RX support)
- Four 10/100/1000 tri-speed Ethernet MAC peripherals with IEEE Std 802.3 and IEEE Std 1588 revision 2.0 support
- Scatter-gather DMA capability
- Recognition of IEEE Std 1588 rev.2 PTP frames o GMII, RGMII, and SGMII interfaces
- Jumbo frames
- Two USB 3.0/2.0 Device, Host, or OTG peripherals, each supporting up to 12 endpoints
- USB 3.0/2.0 compliant device IP core
- Super-speed, high- speed, full-speed, and low-speed modes
- Intel XHCI- compliant USB host
- Two full CAN 2.0B-compliant CAN bus interfaces o CAN 2.0-A and CAN 2.0-B and ISO 118981-1 standard compliant
- Two SD/SDIO 2.0/eMMC4.51 compliant controllers
- Two full-duplex SPI ports with three peripheral chip selects
- Two high-speed UARTs (up to 1Mb/s)
- Two master and slave I2C interfaces
- Up to 78 flexible multiplexed I/O (MIO) (up to three banks of 26 I/Os) for peripheral pin assignment
- Up to 96 EMIOs (up to three banks of 32 I/Os) connected to the PL
Interconnect
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High-bandwidth connectivity within PS and between PS and PL
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Arm AMBA® AXI4-based
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QoS support for latency and bandwidth control
- Cache Coherent Interconnect (CCI)
System Memory Management
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System Memory Management Unit (SMMU)
- Xilinx Memory Protection Unit (XMPU)
Configuration and Security Unit
- Boots PS and configures PL
- Supports secure and non-secure boot modes
System Monitor in PS
- On-chip voltage and temperature sensing
Programmable Logic (PL)
Configurable Logic Blocks (CLB)
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Look-up tables (LUT)
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Flip-flops
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Cascadable adders
36Kb Block RAM
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True dual-port
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Up to 72 bits wide
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Configurable as dual 18Kb
UltraRAM
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288Kb dual-port
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72 bits wide
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Error checking and correction
DSP Blocks
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27 x 18 signed multiply
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48-bit adder/accumulator
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27-bit pre-adder
Programmable I/O Blocks
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Supports LVCMOS, LVDS, and SSTL
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1.0V to 3.3V I/O
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Programmable I/O delay and SerDes
JTAG Boundary-Scan
- IEEE Std 1149.1 Compatible Test Interface
PCI Express
- Supports Root complex and End Point configurations
- Supports up to Gen3 speeds
- Up to five integrated blocks in select devices
100G Ethernet MAC/PCS
- IEEE Std 802.3 compliant
- CAUI-10 (10x 10.3125Gb/s) or CAUI-4 (4x 25.78125Gb/s)
- RSFEC (IEEE Std 802.3bj) in CAUI-4 configuration
- Up to four integrated blocks in select devices
Interlaken
- Interlaken spec 1.2 compliant
- 64/67 encoding
- 12 x 12.5Gb/s or 6 x 25Gb/s
- Up to four integrated blocks in select devices
Video Encoder/Decoder (VCU)
- Available in EV devices
- Accessible from either PS or PL
- Simultaneous encode and decode
- H.264 and H.265 support
System Monitor in PL
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On-chip voltage and temperature sensing
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10-bit 200KSPS ADC with up to 17 external inputs
Zynq UltraScale+ MPSoCs
| CG Devices | EG Devices | EV Devices | |
| APU | Dual-core Arm Cortex-A53 | Quad-core Arm Cortex-A53 | Quad-core Arm Cortex-A53 |
| RPU | Dual-core Arm Cortex-R5 | Dual-core Arm Cortex-R5 | Dual-core Arm Cortex-R5 |
| GPU | – | Mali-400MP2 | Mali-400MP2 |
| VCU | – | – | H.264/H.265 |
More information
The Zynq UltraScale+ MPSoCs are able to serve a wide range of applications including:
- Automotive: Driver assistance, driver information, and infotainment
- Wireless Communications: Support for multiple spectral bands and smart antennas
- Wired Communications: Multiple wired communications standards and context-aware network services
- Data Centers: Software Defined Networks (SDN), data pre-processing, and analytics
- Smarter Vision: Evolving video-processing algorithms, object detection, and analytics
- Connected Control/M2M: Flexible/adaptable manufacturing, factory throughput, quality, and safety
The UltraScale MPSoC architecture provides processor scalability from 32 to 64 bits with support for virtualization, the combination of soft and hard engines for real-time control, graphics/video processing, waveform and packet processing, next-generation interconnect and memory, advanced power management, and technology enhancements that deliver multi-level security, safety, and reliability. Xilinx offers a large number of soft IP for the Zynq UltraScale+ MPSoC family. Stand-alone and Linux device drivers are available for the peripherals in the PS and the PL. Xilinx’s Vivado® Design Suite, SDKTM, and PetaLinux development environments enable rapid product development for software, hardware, and systems engineers. The Arm-based PS also brings a broad range of third-party tools and IP providers in combination with Xilinx's existing PL ecosystem.
The Zynq UltraScale+ MPSoC family delivers unprecedented processing, I/O, and memory bandwidth in the form of an optimized mix of heterogeneous processing engines embedded in a next-generation, high-performance, on-chip interconnect with appropriate on-chip memory subsystems. The heterogeneous processing and programmable engines, which are optimized for different application tasks, enable the Zynq UltraScale+ MPSoCs to deliver the extensive performance and efficiency required to address next-generation smarter systems while retaining backwards compatibility with the original Zynq-7000 All Programmable SoC family. The UltraScale MPSoC architecture also incorporates multiple levels of security, increased safety, and advanced power management, which are critical requirements of next-generation smarter systems. Xilinx’s embedded UltraFastTM design methodology fully exploits the ASIC-class capabilities afforded by the UltraScale MPSoC architecture while supporting rapid system development.
The inclusion of an application processor enables high-level operating system support, e.g., Linux. Other standard operating systems used with the Cortex-A53 processor are also available for the Zynq UltraScale+ MPSoC family. The PS and the PL are on separate power domains, enabling users to power down the PL for power management if required. The processors in the PS always boot first, allowing a software centric approach for PL configuration. PL configuration is managed by software running on the CPU, so it boots similar to an ASSP.
Unsere Tech Map im FPGA
Spezialtools
Vitis/Vivado, Quartus Prime, Diamond, Libero, Matlab
Software-plattformen
NVidia Jetson, Alveo, OpenVINO, TensorFlow, Keras, Caffe
Tools & Sprachen
Verilog, VHDL, VivadoHLS, Simulink/HDL Coder, С/C++, Python
Hardware-Design
High-speed PCBs, DDR4, JESD204b, HDMI, SDI, SI, PI, Thermo modeling
Plattformen
Zynq UltraScale+, RFSoC, Cyclone10, ECP5, MPF500
Transceiver
AD9361, AD9371, ADRV9009, Radars, Custom AFE, Antenas
Netzwerk-protokoll
DPDK, UDP 10G, TCP 10G, TAPs, L1/L2 IP cores
Networking
1G, 10G, 25G/40G, 100G
Unsere FPGA-Designprojekte
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